Input / Output

Input / Output Architecture

Input device:

-Mouse

-Keyboard

-Scanner

-CD-ROM

Output Devices:

-Monitor

-Printer

-Speaker

-Disk Drive

Input output module:

-Interface to CPU and memory

-Interface to one or more periheral

Geberic Model of I/O module:

Function of I/O module:

-Device communication

-CPU communicating

-Control and timing

-Data buffering

-Error detection

                               

Control and Timing:

1) CPU asks I/O module to check the status of attached device.

2) I/O module tells the status.

3) CPU requests for data transfer to I/O module if device is ready.

4) I/O module gathers the data and transfers to the CPU.

Input/Output structure:

Bus Type:

Processor-Memory buses:

◦Short, high speed

◦Design is matched to memory organization

  I/O buses

◦Longer, allowing multiple connections

◦Specified by standards for interoperability

◦Connect to processor-memory bus through a bridge

Bus signal and sycchronization:

Data lines

◦Carry address and data

◦Multiplexed or separate

Control lines

◦Indicate data type, synchronize transactions

Synchronous

◦Uses a bus clock & a fixed protocol for communicating. E.g. perform a read from memory: 1st clock   cycle need a protocol to transmit the address and read command using control lines. 5th clock cycle,  the memory need to respond eith the data word.

◦Adv= fast. Disadv= clock skew and synchronization problem.

 Asynchronous

◦Uses request/acknowledge control lines for handshaking to accommodate a wide variety of devices of differing speed

◦Solve clock skew and synchronization prob.

I/O management:

I/O is mediated by the OS

◦Multiple programs share I/O resources

Need protection and scheduling

◦I/O causes asynchronous interrupts

Same mechanism as exceptions

◦I/O programming is complex

OS provides abstractions to programs

I/O command:

I/O devices are managed by I/O controller hardware

◦Transfers data to/from device

◦Synchronizes operations with software

Command registers

◦Cause device to do something

Status registers

◦Indicate what the device is doing and occurrence of errors

Data registers

◦Write: transfer data to a device

◦Read: transfer data from a device

Techniques of I/O:

i.Programmed I/O : The CPU issues a command then waits for I/O operations to be complete. If the CPU is faster than the I/O module then this method is wasteful of CPU time.

ii.Interrupt Driven I/O : The CPU issues commands then proceeds with its normal work until interrupted by I/O device on completion of its work.

iii.DMA : In this CPU and I/O Module exchange data without involvement of CPU.

iv.Memory mapped I/O : there is a single address space for memory locations and I/O devices. CPU treats the status and data registers of I/O modules as memory locations and uses the same machine instructions to access both memory and I/O devices.

v.Isolated I/O : a dedicated instruction that is used to give a command to an I/O device. It specifies both the device number and the command.

Programmed I/O (Polling):

Periodically check I/O status register

◦If device ready, do operation

◦If error, take action

Common in small or low-performance real-time embedded systems

◦Predictable timing

◦Low hardware cost

In other systems, wastes CPU time

Programmed I/O:

Problems with Programmed I/O:

much time is wasted spin waiting.

if it takes 100 instructions to program this, and each instruction takes 20ns to execute, then it takes

100 * 20nsec = 2000nsec = 2 usec to execute

if a device takes 2msec (=2000usec) to deal with one character, then the percent of time spent waiting

time waiting / total time = 2000us / 2000us +2us =99.9%

We'd like a solution that spent less time "doing nothing"

Interrupt Processing:

Interrupt Driven I/O cycle:

Direct Memory Access:

Special Purpose Processor: DMA controller

◦Free CPU from pure data transfer tasks

◦DMA access: Pointer to source, destination and size of data issued to start transfer

◦Processor writes the data DMA access data and continuous working

◦Handshake protocol

DMA request and DMA acknowledge

DMA controllers are standard components in PCs

I/O Transfer Mode:

Serial

◦In band signaling

◦Bit oriented

◦Bit/byte word translation

Parallel

◦Byte word oriented

◦Out of band signaling

◦IDE, SCSI

Measuring I/O Performance:

I/O performance depends on

◦Hardware: CPU, memory, controllers, buses

◦Software: operating system, database management system, application

◦Workload: request rates and patterns

I/O system design can trade-off between response time and throughput

◦Measurements of throughput often done with constrained response-time

I/O System Design:

Satisfying latency requirements

◦For time-critical operations

◦If system is unloaded

Add up latency of components

Maximizing throughput

◦Find “weakest link” (lowest-bandwidth component)

◦Configure to operate at its maximum bandwidth

◦Balance remaining components in the system

If system is loaded, simple analysis is insufficient

◦Need to use queuing models or simulation

Server Computer:

Applications are increasingly run on servers

◦Web search, office apps, virtual worlds, …

Requires large data center servers

◦Multiple processors, networks connections, massive storage

◦Space and power constraints

Server equipment built for 19” racks

◦Multiples of 1.75” (1U) high