DIGITAL LOGIC SIMULATOR

Digital Logic Simulator

A logic simulator is a computer program that allows designers and experimenters to conduct virtual tests of complex digital circuitry before working with any hardware. The user can interact with the program to find a component arrangement that will perform a desired task.

All digital systems comprise multiple logic gates, often in vast numbers. Some large or sophisticated systems also contain smaller, self-contained digital devices such flip flops, multiplexers, oscillators, integrator, and counters. Each smaller device plays a unique and vital role in the complete system. Digital logic simulator also divides in 2 type logic.

Combinational Logic

A combinational circuit can be defined as a circuit whose output is dependent only on the inputs at the same instant of time where as a sequential circuit can be defined as a circuit whose output depends not only on the present inputs but also on the past history of inputs.

Half adder

Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily constructed using one X-OR gate and one AND gate. Half adder is the simplest of all adder circuit, but it has a major disadvantage. The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry. Below will show the block diagram, truth table and logic circuit.

Figure 1: Half adder - Block diagram

Figure 2: Half adder - Logic Circuit

Figure 3: Half adder - Truth Table

Full adder

Full adder is a little more difficult to implement than a half-adder. A combination of gates in a circuit to add three bits is called a full-adder. The first two inputs are A and B and the third input is an input carry designated as CIN. When full adder logic is designed we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next. The output carry is designated as COUT and the normal output is designated as S. Below will show the block diagram, truth table and logic circuit.

Figure 4: Full adder - Block diagram

Figure 5: Full adder - Logic Circuit

Figure 6: Full adder - Truth Table

Decoder

A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the reverse of encoding, but we will begin our study of encoders and decoders with decoders because they are simpler to design. The name “Decoder” means to translate or decode coded information from one format into another, so a digital decoder transforms a set of digital input signals into an equivalent decimal code at its output.

A common type of decoder is the line decoder which takes an n-digit binary number and decodes it into 2n data lines. The simplest is the 1-to-2 line decoder.

Figure 7: Decoder - Block diagram

Figure 8: Decoder - Logic circuit

Figure 9: Decoder - Truth table

Encoder

Encoders are combinational logic circuits and they are exactly opposite of decoders. They accept one or more inputs and generate a multi bit output code.

Encoders perform exactly reverse operation than decoder. An encoder has D input and X, Y output lines. Out of D input lines only one is activated at a time and produces equivalent code on output N lines. If a device output code has fewer bits than the input code has, the device is usually called an encoder.

Figure 10: Encoder – Block diagram and truth table

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Multiplexer

Multiplexers are generally described as 2N–to–1 devices. These multiplexers have 2N inputs, one of which is connected to the single output line.  The N control lines determine which of the inputs is connected to the output.  Here is a circuit for a 4–to–1 multiplexer.

Figure 11: multiplexer - Block diagram 

Figure 12: Multiplexer - Logic circuit and truth table

Demultiplexer

Demultiplexer means one to many. A demultiplexer is a circuit with one input and many outputs. By applying control signal, we can steer any input to the output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer.

Figure 13: Demultiplexer - Block diagram 

Figure 14: Demultiplexer - Logic circuit 

Figure 15: Demultiplexer - Truth table 

Difference between of multiplexer and demultiplexer

Multiplexer	Demultiplexer
A MUX is a digital switch with that has multiple  inputs (sources) and a single output (destination)	A DEMUX is a digital switch with a single input (source) and a multiple output (destination)
The select lines determine which input is connected to the output.	The select lines determine which output the input is connected to.
MUX Types: -2 to 1 (1 select line) -4 to 1 (2 select lines) -8 to 1 (3 select lines) -16 to 1 (4 select lines)	DEMUX Types: -1 to 2 (1 select line) -1 to 4 (2 select lines) -1 to 8 (3 select lines) -1 to 16 (4 select lines)

Typical application of a MUX:

Typical application of a DEMUX :

Below will show the video about multiplexer and demultiplexer

Sequential logic:

Sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs. This is in contrast to combinational logic, whose output is a function of only the present input. That is, sequential logic has state (memory) while combinational logic does not. Or, in other words, sequential logic is combinational logic with memory. Sequential logic is further divided into synchronous logic and asynchronous logic. As standard logic gates are the building blocks of combinational circuits, bistable latches and flip-flops are the basic building blocks of Sequential Logic Circuits. Sequential logic circuits can be constructed to produce either simple edge-triggered flip-flops or more complex sequential circuits such as storage registers, shift registers, memory devices or counters.

Figure 16: Sequential Logic – Symbol block diagram

Figure 17: Sequential Logic – Symbol block diagram

Synchronous Logic

In synchronous logic, the logic operation is repeated cyclically through an oscillating signal supplied to every flip-flop in the circuit. This signal, often called the clock pulse, activates the logic circuit for a single operation.

The main advantage of synchronous logic is its simplicity. The main disadvantages of synchronous logic are the limited clock speed available and the requirement of a clock signal for every flip-flop. As a result, the speeds of the synchronous circuits are limited and energy wastage occurs when distributing the signal to every flip-flop element.

Figure 18: Synchronous Logic – Symbol block diagram

Asynchronous Logic

In asynchronous logic, all the flip flops are not clocked at the same cycle. Rather, each individual flip-flop is clocked through the main clock signal or by an output of another flip-flop. Therefore, the speeds of the asynchronous logic circuits are much higher than the synchronous circuits. Even though asynchronous logic is efficient, they are difficult to design and implement and pose problems if two signals overlap.

Figure 19: Asynchronous Logic – Symbol block diagram

Flip-Flop

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do.

All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. The four types of flip-flops are defined in Table 1.

Table 1: Types of Flip-Flop

SR Flip-flop - (Set / Reset)

The SR flip-flop is one of the best known and simplest circuits for storing a bit-information. On Picture 1 are shown the symbol, the schematic symbol and the table of truth of SR flip-flop. The inputs of the circuit are marked with S (set) and R (reset). The outputs are Q and its negation. When we send a pulse on the input S, then we say that the circuit is set. When we send a pulse on the input R, then we say that the circuit is reset. Q' is inverse state of the state of Q (when Q is true, Q' is false). If the inputs S and R are both 0, then the outputs remains the same as the last set or reset to the circuit. As we can see from the table of truth, if S = 1 and R = 0, then output Q = 1. In other case, if S = 0 and R = 1, then output Q = 0. However, if both of the inputs S and R are 1, then the output of the circuit is unpredictable and because of that the state when S = 1 and R = 1 is not allowed.

Figure 20: SR Flip Flop – Symbol, Schematic symbol and truth table

D Flip-flop

The input of this circuit is marked as D (data). The symbol of the D Flip-flop an its table of truth are shown on Picture 2. The other input of the circuit, which signed as >, is actually the clock signal (clk). The logic state of the input D is send to the output only if there is a positive pulse on the clock input. If there is a change of the state of the input D, this change will be not send to the output Q until the next positive pulse of the clock signal.

Figure 21: D Flip-Flop – Symbol and truth table

T Flip-Flop

The symbol of the T Flip-flop an its table of truth are shown on Picture 3. The output of this circuit is changing its state for every positive pulse from the clock signal that is send to the input T. This means that the output signal of this circuit have two times lower frequency from the frequency of the input (clock) signal. So, this circuit can be used for dividing the frequency of the input clock signal with ratio 2:1. If we connect two of this circuit in series, then we will have the dividing with ratio 4:1, etc.

Figure 22: T Flip Flop – Symbol and truth table

JK Flip-Flop

This circuit has two inputs marked as J and K. The third input (>) is for the clock signal. On Picture 4 are shown the symbol of the JK Flip-flop an its table of truth. If input J = 1 and input K = 0, then when the clock signal have the positive pulse the output Q is set (Q = 1). If J = 0 and K = 1, then in case of the positive pulse of the clock signal the output Q is reset (Q = 0). In the case when both of the inputs J and K are 1, then in case of the positive pulse of the clock signal the output Q is changing its state. And finally, when both of the inputs J and K are 0, then in case of the positive pulse of the clock signal the output Q doesn't change its state. The advantage of this circuit is that there is no unpredictible state as in the case of the RS flip-flop.

Figure 23: JK Flip Flop – Symbol and truth table

Below was showed the video about Flip-Flop

Latches

A latch is an example of a bistable multivibrator, that is, a device with exactly two stable states. These states are high-output and low-output. A latch has a feedback path, so information can be retained by the device. Therefore latches can be memory devices, and can store one bit of data for as long as the device is powered. As the name suggests, latches are used to "latch onto" information and hold in place. Latches are very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges as flip-flops do.

SR Latch

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR latch.

Figure 24: Circuit symbol for an SR latch.

Figure 25: An SR latch made from two NOR gates.

Figure 26: An SR latch made from two NAND gates.

Figure 27: SR Latch – truth table

D latch

The D latch (D for "data") or transparent latch is a simple extension of the gated SR latch that removes the possibility of invalid input states.

Since the gated SR latch allows us to latch the output without using the S or R inputs, we can remove one of the inputs by driving both the Set and Reset inputs with a complementary driver: we remove one input and automatically make it the inverse of the remaining input.

The D latch outputs the D input whenever the Enable line is high, otherwise the output is whatever the D input was when the Enable input was last high. This is why it is also known as a transparent latch - when Enable is asserted, the latch is said to be "transparent" - it signals propagate directly through it as if it isn't there.

Figure 28: D latch - A gated SR latch extended to prevent invalid output conditions

Figure 29: D Latch – truth table

Difference between Latches and Flip Flops

Latches	Flip Flops
Ø is an asynchronous bistable multivibrator circuit	Ø Is a synchronous bistable multivibrator circuit.
Ø the retained state can change at any instant when the enable is at the high state	Ø The retained state can change only at the rising edge or the falling edge of the clock signal given as the input of the enable.

Difference between combinational logic and sequential logic:

Combinational Logic	Sequential Logic
Ø Uses only the present inputs to determine the output	Ø Uses both present inputs as well as previous outputs to determine the current input.
Ø Used to implement basic Boolean operations	Ø used to create memory elements
Ø Does not require feedbacks.	Ø uses the feedbacks from the output to inputs
Ø  It contains no memory elements	Ø  It contains memory elements

Published By : SAW WAN SYNN B031410008

Section : 1-BITD / S1G1